• 出版社/出版日：Mordor Intelligence / 2021年2月15日
The panel level packaging (PLP) market is anticipated to register a CAGR of 28.0% over the forecast period from 2021 to 2026. Panel Level Packaging (PLP) has been expected to become a critical packaging process. Manufacturers are increasingly driving their suppliers to provide panel -processing tools and materials to allow them to bring wafer-level precision to packaged processed on panel substrates. This packaging is used in the packaging of field-programmable gate array (FPGA), CPU/GPU, power management IC module, baseband, and others. The solution provides to reduce the cost of circuit packaging and enhances design flexibility.
– The latest trend in the packaging is Fan-out packaging, which is the promising area of market advancement in the global semiconductor packaging industry. Players such as ASE, Powertech, Nepes, and Samsung are looking forward to panel -level packaging, providing economies of scale. These companies are developing or ramping up panel-level fan-out packaging to reduce the cost of advanced packaging. Wafer-level fan-out is one of the several advanced packaging types where packages can incorporate dies, MEMS, and passives in a single IC package. This approach has been in production for many years and is produced in a round wafer format in 200mm or 300mm wafer sizes.
– Players such as Mi Technovation Bhd are primarily involved in the design, manufacturing, and sale of the wafer level chip scale package and sorting machines with the inspection and testing capabilities for the semiconductor industry. Further, TSMC (Taiwan Semiconductor Manufacturing Company) announced in October 2019 that it would increase its Capex by 40% to USD 14 billion in 2020, providing advanced solutions in the panel packaging. As, wafer and panel level packaging (WLP/PLP) have the potential to offer more cost-effective packaging solutions for specific applications, in April 2020, iNEMI’s Wafer/Panel Level Package Flowability and Warpage project announced that they are focused on increasing understanding of the molding process and developing simulation approaches.
– South Korea’s semiconductor industry is continuing to put in efforts to improve and to make 3D TSV (Through – silicon via), packaging and FoWLP (Fan-out Wafer -Level Packaging), and FoPLP (Fan-out Panel -Level Packaging) technologies more effective to raise the performance of semiconductors and the degree of integration. In October 2019, KOSTEK SYSTEM had developed a temporary wafer bonder and debonding systems called TAURUS-300FOB and TAURUS-300FOD that are for semiconductor fan-out packaging process and can be applied to both FoWLP and FoPLP technologies. It has supplied both of the systems to South Korean companies. Because South Korean companies had depended on foreign companies for these systems in the past, KOSTEK is expecting a considerable import substitution effect in the future.
– Further, with the recent outbreak of COVID-19, the PLP packaging market will witness a decline in growth due to restrictions on the movement of goods and severe disruptions in the semiconductor supply chain. Moreover, the major semiconductor vendors are working with reduced capacity owing to the spread of COVID-19 virus across the world. For instance, Foxconn iPhone production operations located about 300 miles from Wuhan in Zhengzhou operated with 10-20 % capacity due to workforce issues by the lockdown of cities. South Korea’s chip exports for May rose 7.1 % from a year earlier, as working from home trends and online classes boosted demand for servers and PCs. Chinese PC makers recovered production, driving up chip prices, according to a trade ministry.
Key Market Trends
Consumer Electronics is Expected to Hold Major Share
– Mobile consumer electronics are powering a new wave of developments in electronic packaging. In the United States, with increasing consumer electronic sales year on year, the demand for panel-level packaging significantly rises. Further, Berlin’s Fraunhofer IZM is the place to be for leading industry players wishing in developing the fundamental processes for the new panel-level packaging and creates viable first demonstrators on large-scale organic substrate formats in the consumer electronics. After the successful venture for two years, the consortium is focused on embracing new members with new research avenues.
– Moreover, at the start of 2020, TSMC was investing heavily in 5nm fabrication. TSMC’s 7nm process is at its peak, receiving vast numbers of orders from AMD for its Ryzen 3000-series CPUs and Navi graphics cards and other customers, including Apple and Huawei. On the 5nm front, TSMC is working with EUV lithography, similar to what Samsung is accomplishing, and the company expects 10% of 2020’s year’s revenue to come from its 5nm EUV lines. After the 3nm process takes over, TSMC expects mass production to start in 2022. This significantly drives the market in the future period.
– Also recently, SEMCO achieved a new milestone by rolling out APE-PMIC devices with FO (Fan-Out) embedded panel-level packaging (ePLP) PoP technology for Samsung Galaxy Watch. SEMCO announced to continue to innovate for a cost-effective HDFO market space to compete with TSMC for Apple’s packaging and FE business again. In years to come, SEMCO’s HDFO is anticipated to be utilized first in Samsung’s cellphones. Besides, a restructure between SEMCO, and Samsung Electronics could be favorable for Samsung’s position as the full turnkey provider for a FE+BE bundle.
– However, due to work from home culture started during the pandemic, the demand for personal computers is significantly increasing. In June 2020, Samsung Electronics Co Ltd announced that they begun construction of a new domestic production line for NAND flash memory chips, betting on demand for personal computers and servers as the coronavirus prompts more people to work from home. Samsung mentioned that the additional capacity would also help meet the demand for 5G smartphones and other devices despite recent delays in deployments of 5G networks in Europe and other countries due to pandemic. The production line for NAND memory significantly raises the demand for panel-level packaging currently.
North America is Expected to Hold Significant Share
– North America is expected to reflect significant growth in the market due to the high adoption of consumer electronics, advanced technology integration in the automotive, and further with various players who focused on investing in the region. The researchers in the region are extensively investing in product innovations using MEMS. California-based MEMS Drive announced to partner with SmartSens Technology to integrate MEMS with image sensing chips for achieving chip-level optical image stabilization (OIS) to extend its application in security monitoring, AI, ML, and autonomous vehicles. This significantly drives the packaging in MEMS for the hermetically sealed and reliable packaging solutions.
– The United States leads the world in manufacturing, designing, and researching concerning the semiconductor industry. The country is also the frontrunner in semiconductor packaging innovation, boasting of 80 wafer fabrication plants spreading across its 19 states. Further, in March 2020, Taiwan Semiconductor Manufacturing Co, has joined forces with US-based IC design house Broadcom Inc. to develop the advanced 5 nanometers (nm) process. TSMC announced it has teamed up with Broadcom to bolster its chip-on-wafer-on-substrate (CoWoS) IC packaging platform that supports 5nm technology.
– Further, as the panel level processing incorporates a mix of LCD, PCB, wafer-level, and others, which leads to complicated industry landscape, SEMI Standards Panel Level Packaging Panel Task Force conducted the push towards the standardization of single panel size across a variety of different materials and different processes. This standardization enables a single toolset for panel level processing, whether chip first or chip last, whether on the substrate or utilizing a carrier. During adjudication, at the SEMI Standards 3D Packaging & Integration North America Technical Committee Chapter Spring 2019 Meetings, the ballot was presented to improve standardization.
– Also, players are innovating new packaging solutions along with acquisition that significantly helps in driving the market. In July 2019, TDK America showcased AFM 15 Flip Chip GGI Die Bonder and PLP Load Port at SEMICON West 2019. AFM 15 for GGI flip-chip back end assembly packaging allows for die-sized capability 80μm2 ~ 20mm2, low energy dies bonding, a clean, lead-free process, and high productivity. Furthermore, in November 2019, Quik -Pak, announced it acquired Santa Clara -based QBBS for broadening its portfolio of the wafer -preparation services. This addition of QBBS’s automated capability enables Quik-Pak in processing customer wafers in large volumes. Quik-Pak will integrate the QBBS technology into its wafer prep line in 2020.
As few players are dominating the market with their technological expertise in level packaging technology, the global market for panel level packaging is expected to be consolidated in nature. Amkor Technology, Inc., Deca Technologies, Lam Research Corporation, ASE Group, and Taiwan Semiconductor Manufacturing Company Limited are some of the major players in the current market. However, giant chip manufacturers such as Intel Corporation, Qualcomm Technologies, Inc., are involved in extensive R&D and market development activities to develop competitive panel level packaging technology in the coming years.
– May 2020 – Taiwan Semiconductor Manufacturing (TSMC) announced plans to build a USD 12 billion factory in Arizona with support from the state and the US government. TSMC said the plant would be able to produce 20,000 semiconductor wafers a month, directly employing more than 1,600 people.
– October 2019 – Deca Technologies has reached an agreement with nepes Corporation whereby nepes will expand its geographic footprint and manufacturing capabilities by taking over the operations of Deca Technologies’ Philippines manufacturing facility.Nepes acquired the fan-out manufacturing line from Deca. Nepes also licensed Deca’s wafer and panel level fan-out technology.
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1.1 Study Assumptions and Market Definition
1.2 Scope of the Study
2 RESEARCH METHODOLOGY
3 EXECUTIVE SUMMARY
4 MARKET DYNAMICS
4.1 Market Overview (Assessment with COVID-19 Impact)
4.2 Introduction to Market Drivers and Restraints
4.3 Market Drivers
4.3.1 Reduced Cost of Packaging Process
4.3.2 Enhanced Design Flexibility and Physical Performance of Chips
4.3.3 Increased Investment on Research & Development Activities
4.4 Market Restraints
4.4.1 Complexity in Packaging Process
4.5 Industry Value Chain Analysis
4.6 Industry Attractiveness – Porter’s Five Force Analysis
4.6.1 Threat of New Entrants
4.6.2 Bargaining Power of Consumers
4.6.3 Bargaining Power of Suppliers
4.6.4 Threat of Substitute Products
4.6.5 Intensity of Competitive Rivalry
5 MARKET SEGMENTATION
5.1 Industry Application
5.1.1 Consumer Electronics
5.1.3 Aerospace & Defence
5.1.5 Other Industry Application
5.2.1 North America
5.2.4 Rest of the World
6 COMPETITIVE LANDSCAPE
6.1 Company Profiles
6.1.1 Amkor Technology, Inc.
6.1.2 Deca Technologies
6.1.3 Lam Research Corporation
6.1.4 ASE Group
6.1.5 Siliconware Precision Industries Co., Ltd.
6.1.6 Fraunhofer Institute for Reliability and Microintegration IZM
6.1.7 Taiwan Semiconductor Manufacturing Company, Limited
6.1.8 Shinko Electric Industries Co, Ltd.
7 INVESTMENT ANALYSIS
8 MARKET OPPORTUNITIES AND FUTURE TRENDS